Static timing analysis refers to the method of verifying the timing behavior of a digital circuit without applying exhaustive test patterns. This is usually done by constructing a timing graph to capture the underlying temporal behavior of the digital circuit and analyzing the timing graph for any potential problems or timing violations. The timing graph consists of timing pins and edges that connect the pins. The timing analysis can be done by traversing the timing graph and computing arrival times (AT) of signals relative to some clock signals and required times (RT) at relevant pins. ATs are computed by traversing the timing graph from inputs towards outputs and RTs from outputs towards inputs. The setup slack is defined as RT minus AT. If a signal arrives before (respectively, after) it is required at some pin, the pin is said to have a positive (respectively, negative) slack. Another term used in static timing analysis is “hold slack” defined as AT minus RT, and indicates the margin by which a signal remains present at a particular end point for a particular timing event, after it is needed.
After a digital circuit has been designed, its static timing typically must pass a signoff test. The principal software used for performing a signoff static timing analysis test (henceforth “time test”) is Synopsys® PrimeTime® static timing software, although there are other static timing analysis programs that are also used for a signoff test. The signoff software may not be easily available to the circuit designer, and could take as long as a full day to run in the mode which yields the most accurate result. Accordingly, it is not uncommon for the circuit designer to use a basic static timing analysis test that uses less runtime and less expensive software or uses the standard software in a faster running but less accurate mode, as he proceeds through the iterations of his design When the term “time test” is used in this application it means a static timing analysis test done for design development purposes or for static timing analysis signoff Unfortunately, when the circuit is developed to the point where it is ready for the signoff time test, there is a good chance that it will fail because of differences between the basic time test and the signoff time test. When this happens, costly redesign must be performed.
Accordingly, there is a need for a method of using a basic static time test to more accurately guide the effort to develop a digital circuit with an enhanced chance of passing the signoff time test, together with the other criteria the circuit must meet.